1. Field of the Invention
This invention relates to integrated circuits, and particularly to metal oxide semiconductor large scale integrated circuit (MOS/LSI) devices having n-channel or p-channel MOS field effect transistors, such as are commonly used in hand calculators, home and office computers, automotive and industrial control systems, games, and other commercial products. MOS/LSI devices use numerous circuit designs to achieve specific functions. One of the circuit designs used in MOS/LSI devices is a time delay circuit, i.e., a circuit which provides an output signal delayed by a predetermined time from the occurrence of an input signal. A time delay circuit designed for use in MOS/LSI devices should be relatively insensitive to process variations and variations in temperature. The invention circuit provides these features and is particularly suitable for manufacture by standard integrated circuit processing steps.
2. Description of the Prior Art
The most common time delay circuit used in MOS/LSI device design consists of a string of simple inverters. These inverters are generally used in tandem pairs to provide a delayed noninverted output signal in response to an input signal. Each inverter circuit is comprised of a depletion mode field effect transistor connected between a voltage source, such as VDD, and the output of the circuit, the depletion mode field effect transistor having its gate connected to its source and correspondingly the output of the inverter circuit. The output of the inverter circuit is connected to ground through an enhancement mode field effect transistor, the input of the circuit being connected to the gate of this enhancement mode field effect transistor. To increase the delay afforded by an inverter circuit, capacitance is formed on the output of the inverter. By increasing the amount of this capacitance and by concurrently decreasing the conductivity of the pull up depletion mode field effect transistor, additional delay per inverter circuit is obtained. Large delays are obtained by designing the required number of pairs of inverter circuits into the time delay circuit to obtain the desired delay.
The above referenced prior art delay circuit is sensitive to temperature and process variations. In addition, the above referenced prior art circuit design requires a relatively large number of components to obtain even small time delays.